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@nousername@lemmus.org

2026-11-01 23:14 UTC

lol. That whole thing was propaganda. First of all, the 4F2 process isn’t better than the 6F2 process. 4F2 is worse! 4F2, just means they’re being forced to build the chip vertically in more steps because they don’t have access to ASMLs most advanced lithography machines. Because they can’t pack more transistors into a smaller space by making them smaller, they’re being forced to build them vertically, which requires more layers. And more layers means more chances for microscopic mistakes. And that’s the case! Their yields are abysmal, only 30% yields, while Samsung and SK Hynix typically get 70% yields. And what do 30% yields mean? It’s means the process isn’t commercially viable. The only reason it even exists is because the Chinese government forces it to. In order to be commercially viable, their prices would have to be much higher than everyone else’s, in which case it’s a huge waste of time. Granted, the Chinese government might flood the world with these chips as a loss leader, but mostly they’re just making them to satisfy the Chinese government’s own need for chips. They probably won’t leave the country in any significant number.

Replies (1)

  • @avidamoeba@lemmy.ca 2026-11-02 05:49

    Hm. This says their 17nm DDR5 yields have surpassed 90%. HBM3E yields appears to be low. 4F2 targets 10nm DRAM which doesn’t require ASML’s most advanced stuff - EUV, AFAIK. It’s done with DUV which China has plenty of and they also got some domestic machines coming out this year. I see info that Micron has pivoted away from 4F2 but SK and Samsung are actively developing it for their next processes. Do you have anything that shows otherwise? If they’re still developing it, why would they do it if 4F2 is worse than 6F2?

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